Publication
A-SSCC 2014
Conference paper

A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm2 in 32 nm SOI CMOS

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Abstract

An area- and power-optimized asynchronous 32× interleaved SAR ADC achieving 36 GS/s at 110mW with 1V supply on the interleaver and 0.9 V on the SAR ADCs is presented. The ADC features a 2-channel interleaver with data demultiplexing for enhanced bandwidth, a power- and area-optimized binary SAR ADC, and an area-optimized clocked reference buffer with a tunable constant-current source. It achieves 32.6dB SNDR up to 3GHz and 31.6dB up to 18GHz input frequency and 98fJ/conversion-step with a core chip area of 340×140μm2 in 32nm SOI CMOS technology.

Date

13 Jan 2015

Publication

A-SSCC 2014

Authors

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