High performance processors and ASICs typically require multiple voltages and multi-domain voltage controls across the die. Conventional approaches distribute the voltage regulation elements between the processor, the package laminate, and the printed circuit board. We propose an alternative approach where the voltage regulator is embodied in a 3D configuration such that the inductor, capacitor and the switches are formed on a separate silicon chip sandwiched between the processor and the laminate. Due to the close proximity of regulator to the processor, this approach can enable granular voltage domains, while minimizing disruptions to the processor layout. We describe a 4-f DC-DC buck converter fabricated on 32nm SOI wafers using TSVs to connect the switches on the front-side of the wafer to the inductors on the grind-side. The process builds on a 32nm SOI CMOS flow, adding deep trench (DT) capacitors and TSV's. Down conversion from a standard I/O voltage under various load conditions was evaluated, and an efficiency of 77% was achieved.