Flip-chip assembly with self-Alignment down to sub-micron accuracy opens the door for low-cost assembly of micro-photonic chips. The surface tension of melted solder can be used to bring chips into alignment. The use of lithographically defined mechanical structures to stop the solder induced movement provides sub-micron alignment accuracy. However, several factors can impact the solder re-Alignment yield. In this paper, we investigate the various yield limiting contributors and show that sensitivity to solder volume is the dominating factor. Variation in the amount of solder strongly impacts the lateral and vertical force induced by the solder, resulting in two small a process window for manufacturability. We show through models and experiments a design-based solution that dramatically improves the process window and yield. By the addition of local solder "reservoirs» we create a self-balanced system to improve solder plating tolerances from just a few percent to nearly a factor of two.