Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications
- J. Zhang
- S. Pancharatnam
- et al.
- 2019
- IEDM 2019
Dr. Dan J. Dechene is Director of Semiconductor Enablement in IBM. He leads IBM's Semiconductor Enablement strategy across IBM Research labs including Yorktown Heights, NY, Albany, NY, Almaden CA, and Burlington, VT. His mission spans design & system technology co-optimization, PDK development, computational patterning leadership, testsite design & mask tapeout. He's also responsible for IBM Semiconductors overall EDA strategy & roadmap.
Dr. Dechene received his Masters (2008) & PhD (2011) degrees in Electrical Engineering at the University of Western Ontario (Canada) following his undergraduate degree at Lakehead University (Canada).
Dan began his career at IBM in East Fishkill, NY focused on advanced patterning techniques, design-technology co-optimization and jointly defining IBM's captive maskhouse requirements roadmap. He's successfully supported delivery on number of IBM technologies focused on computational patterning development. Over the course of his career, he's developed leadership experience in business development and delivering value to partners and clients. Following IBM's Microelectronics divestiture in 2015, Dan was responsible for leading the overall technology definition mission for 7nm and derivatives for Globalfoundries. He was responsible for driving internal and external Fabless engagements and internal/external IP engagements.
Dr. Dechene rejoined IBM in Albany in 2018 where he came in to lead and accelerate IBM's leadership in DTCO for advanced technology R&D. His early major focus was on developing advanced capabilities to rapidly assess technology elements, and features for 1nm and beyond technology. Since that time, Dan has lead building up a broad swath of leadership capabilities in overall Technology Definition. Dan was appointed as Director of Technology Enablement in 2023.
Dan holds a number patents and publications in technical journals and conferences. Dan also serves as committee member for DTCO & Computational Patterning for SPIE Advanced Lithography since 2021.