Vertical-Transport Nanosheet Technology for Scaling beyond the Lateral-Transport Devices CMOS Era
- Hemanth Jagannathan
- Susan Fan
- et al.
- 2023
- SSDM 2023
Bio
Brent Anderson has been part of IBM’s Semiconductor Research and Development team for over 30 years. During this time, the IBM team has delivered new and innovative semiconductor technology elements including Copper Interconnects, Silicon on Insulator Devices, High-K Gate Dielectrics, Embedded DRAM, FINFET Devices, and soon to be introduced into production Lateral Nanosheet Devices.
Brent has made many key contributions towards IBM’s innovation pipeline and is a Lifetime Master Inventor with > 500 patents covering semiconductor devices, manufacturing processes, and design elements. As the lead architect of IBM’s new Vertical Transport Nanosheet (VTFET) technology since its inception, he has driven the program through many phases of hardware and design development and recently presented at the IEDM conference.
Publications
Next-Generation Logic Design Architecture for Vertical-Transport Nanosheets
- Biswanath (Biswa) Senapati
- Jeongho Do
- et al.
- 2023
- SPIE Advanced Lithography + Patterning 2023
Hardware Based Performance Assessment of Vertical-Transport Nanosheet Technology
- Gen Tsutsui
- Seunghyun Song
- et al.
- 2022
- IEDM 2022
Patents
- US
- 11830774
- US
- 11823998
- US
- 11804406
- US
- 11791258
- TW
- I818648
- US
- 11764298
- US
- 11710666
- US
- 11688775
- US
- 11670542
- US
- 11658116
Blog posts
VTFET: The revolutionary new chip architecture that could keep Moore’s Law alive for years to come
NewsBrent Anderson and Hemanth Jagannathan5 minute read- Intelligent Fab
- Logic Scaling
- Semiconductors
Top collaborators
HJ
Hemanth Jagannathan
IBM Distinguished Engineer - Chiplet and Advanced Packaging Technology & Quantum 300mm Scale-out
HB
Huiming Bu
Vice President: IBM Semiconductors Global R&D and Albany Operations
TW
Teresa Wu
Program Director, Semiconductors
DG
Dechao Guo
Director, Advanced Logic Technology Research