Improved manufacturability of Cu bond pads and implementation of seal design in 3D integrated circuits and packages
- K.N. Chen
- C. Tsang
- et al.
- 2006
- VMIC 2006
Publications
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178 results for Wilfried Haensch
Investigation of FinFET devices for 32nm technologies and beyond
- H. Shang
- L. Chang
- et al.
- 2006
- VLSI Technology 2006
Simulation study on channel length scaling of high performance partially depleted metal gate and poly gate SOI MOSFETs
- Wang Xinlin
- Andres Bryant
- et al.
- 2006
- SISPAD 2006
Stable SRAM cell design for the 32 nm node and beyond
- Leland Chang
- David M. Fried
- et al.
- 2005
- VLSI Technology 2005
Effect of contact liner stress in high-performance FDSOI devices with ultra-thin silicon channels and 30 nm gate lengths
- D. Singh
- J. Hergenrother
- et al.
- 2005
- IEEE International SOI Conference 2005
Compact modeling of FinFETs featuring independent-gate operation mode
- C.-H. Lin
- X. Xi
- et al.
- 2005
- VLSI Technology 2005
Three dimensional CMOS devices and integrated circuits
- Meikei Ieong
- Kathryn W. Guarini
- et al.
- 2003
- CICC 2003
Analysis and modeling methodology of strained-Si channel-on-insulator (SSOI) MOSFETs
- Keunwoo Kim
- Ching-Te Chuang
- et al.
- 2003
- VLSI-TSA 2003
Fully On-Chip MAC at 14 nm Enabled by Accurate Row-Wise Programming of PCM-Based Weights and Parallel Vector-Transport in Duration-Format
- Pritish Narayanan
- Stefano Ambrogio
- et al.
- 2021
- IEEE T-ED
Analysis of Effect of Weight Variation on SNN Chip with PCM-Refresh Method
- A. Nomura
- M. Ito
- et al.
- 2019
- Neural Processing Letters