35nm SOI-CMOS for sub-ambient temperature operation

Abstract

We demonstrate over 40% CMOS performance gain with minimal process changes by lowering the operating temperature from 100°C to -50°C For the same performance, the lower temperature operation delivers a 60% reduction in power-delay product at a reduced supply voltage. Coupled with recent advances in liquid cooling techniques, our results suggest that sub-ambient temperature operation is an attractive option for high performance and energy-efficient CMOS. © 2007 IEEE.