A High-Speed 128-kb MRAM Core for Future Universal Memory Applications

Abstract

A 128-kb magnetic random access memory (MRAM) test chip has been fabricated utilizing, for the first time, a 0.18-μm V DD = 1-8 V logic process technology with Cu metallization. The presented design uses a 1.4-μm 2 one-transistor/one-magnetic tunnel junction (1T1MTJ) cell and features a symmetrical high-speed sensing architecture using complementary reference cells and configurable load devices. Extrapolations from test chip measurements and circuit assessments predict a 5-ns random array read access time and random write operations with <5-ns write pulse width.