Publications

30 results for Joel Silberman

High-speed, power-conscious circuit design techniques for high-performance computing
- - O. Takahashi
  - S. Dhong
  - et al.
- 2001
- VLSI-TSA 2001
A 1GHz single-issue 64b powerPC processor
- - H.P. Hofstee
  - Naoaki Aoki
  - et al.
- 2000
- ISSCC 2000
1.6 ns access, 1 GHz two-way set-predicted and sum-indexed 64-kByte data cache
- - Joel Silberman
  - Naoaki Aoki
  - et al.
- 2000
- VLSI Circuits 2000
'Timing Closure by Design,' a high frequency microprocessor design methodology
- - S.D. Posluszny
  - Naoaki Aoki
  - et al.
- 2000
- DAC 2000
High speed serializing/de-serializing design-for-test method for evaluating a 1 GHz microprocessor
- - D. Heidel
  - S. Dhong
  - et al.
- 1998
- VTS 1998
Design methodology for a 1.0 GHz microprocessor
- - S.D. Posluszny
  - Naoaki Aoki
  - et al.
- 1998
- ICCD 1998
690ps read-access latency register file for a GHz integer microprocessor
- - O. Takahashi
  - Joel Silberman
  - et al.
- 1998
- ICCD 1998
1.0-GHz single-issue 64-bit PowerPC integer processor
- - Joel Silberman
  - Naoaki Aoki
  - et al.
- 1998
- IEEE Journal of Solid-State Circuits
1 GHz logic circuits with sense amplifiers
- - O. Takahashi
  - Naoaki Aoki
  - et al.
- 1998
- VLSI Circuits 1998
Designing for a gigahertz
- - H. Peter Hofstee
  - Sang H. Dhong
  - et al.
- 1998
- IEEE Micro