High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- S. Narasimha
- K. Onishi
- et al.
- 2006
- IEDM 2006
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7 results for G. Larosa
Oxygen vacancy traps in Hi-K/Metal gate technologies and their potential for embedded memory applications
- C. Kothandaraman
- X. Chen
- et al.
- 2015
- IRPS 2015
Intrinsic dielectric stack reliability of a high performance bulk planar 20nm replacement gate high-k metal gate technology and comparison to 28nm gate first high-k metal gate process
- W. McMahon
- C. Tian
- et al.
- 2013
- IRPS 2013
Copper through silicon via (TSV) for 3D integration
- C. Kothandaraman
- B. Himmel
- et al.
- 2012
- IRPS 2012
Interface state generation in pFETs with ultra-thin oxide and oxynitride on (100) and (110) Si substrates
- J.H. Stathis
- R. Bolam
- et al.
- 2005
- INFOS 2005
Broad energy distribution of NBTI-induced interface states in p-MOSFETs with ultra-thin nitrided oxide
- J.H. Stathis
- G. LaRosa
- et al.
- 2004
- IRPS 2004
Broad energy distribution of NBTI-induced interface states in p-MOSFETs with ultra-thin nitrided oxide
- J.H. Stathis
- G. Larosa
- et al.
- 2004
- IRPS 2004