NanoStack Transistor Architecture for CMOS 7A Node and Beyond
- S. Reboh
- C. Zhang
- et al.
- 2025
- VLSI Technology and Circuits 2025
Conference paper
Publications
60 results for Hemanth Jagannathan
D2W and W2W Hybrid bonding system with below 2.5 micron pitch for 3D chiplet AI applications
- Katsuyuki Sakuma
- Roy Yu
- et al.
- 2024
- IEDM 2024
Invited talkVertical-Transport Nanosheet Technology for Scaling beyond the Lateral-Transport Devices CMOS Era
- Hemanth Jagannathan
- Susan Fan
- et al.
- 2023
- SSDM 2023
Invited talkManufacturing Yield Improvement for Advanced CMOS Technology Middle-of-Line Interconnect with Cobalt Metallization : YE: YieldEnhancement/Learning
- Susan Fan
- P. Jamison
- et al.
- 2023
- ASMC 2023
Conference paperNext-Generation Logic Design Architecture for Vertical-Transport Nanosheets
- Biswanath (Biswa) Senapati
- Jeongho Do
- et al.
- 2023
- SPIE Advanced Lithography + Patterning 2023
Invited talkHardware Based Performance Assessment of Vertical-Transport Nanosheet Technology
- Gen Tsutsui
- Seunghyun Song
- et al.
- 2022
- IEDM 2022
Invited talkVertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices
- H. Jagannathan
- B. Anderson
- et al.
- 2021
- IEDM 2021
Conference paperStructural and Electrical Demonstration of SiGe Cladded Channel for PMOS Stacked Nanosheet Gate-All-Around Devices
- Shogo Mochizuki
- B. Colombeau
- et al.
- 2020
- VLSI Technology 2020
Conference paperBEOL compatible high-capacitance MIMCAP structure using a novel high k material
- P. Jamison
- John Massey
- et al.
- 2020
- IMCS 2020
Conference paperHigh quality interfacial layer formation for Si0.75Ge0.25 (100) high-k metal gate stack
- S. Siddiqui
- R. Galatage
- et al.
- 2020
- Microelectronic Engineering
Paper