3.5ns CMOS 64K ECL RAM at 77°K
- S.E. Schuster
- T.I. Chappell
- et al.
- 1988
- VLSI Circuits 1988
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5 results for James W. Allan
6.2 ns 64Kb CMOS RAM with ECL interfaces
- T.I. Chappell
- S.E. Schuster
- et al.
- 1988
- VLSI Circuits 1988
A 2-ns Cycle, 3.8-ns Access 512-kb CMOS ECL SRAM with a Fully Pipelined Architecture
- Terry I. Chappell
- Barbara A. Chappell
- et al.
- 1991
- IEEE Journal of Solid-State Circuits
A 3.5-ns/77 K and 6.2-ns/300 K 64K CMOS RAM with ECL Interfaces
- Terry I. Chappell
- Stanley E. Schuster
- et al.
- 1989
- IEEE Journal of Solid-State Circuits
Fast CMOS ECL Receivers with 100-mV Worst-Case Sensitivity
- Barbara A. Chappell
- Terry I. Chappell
- et al.
- 1988
- IEEE Journal of Solid-State Circuits