VLSI Circuits 1988
Conference paper

6.2 ns 64Kb CMOS RAM with ECL interfaces


A sub-10-ns 0.5-μm effective length 64Kb CMOS RAM with ECL interface signals and performance exceeding that of any reported BiCMOS RAM is discussed. High performance with ECL interfaces and robust margins is achieved through innovative CMOS circuit design and a selectively scaled 0.5-μm Leff CMOS process.