Fast CMOS ECL Receivers with 100-mV Worst-Case Sensitivity

Abstract

CMOS ECL receiver circuits consisting of a differential-amplifier stage and a CMOS inverter are shown to convert 100-mV input signals to on-chip CMOS levels even with worst-case parameter variations in a 5-V 1-üm technology. The same ECL receivers in submicrometer CMOS technology have higher speeds and better sensitivity, with smaller worst-case-to-best-case variations. Two different receiver circuits are used to cover a range of power supply options; a third circuit provides a comparison case. The differential amplifiers feature built-in feedback compensation for common-mode parameter variations. The differential input devices are designed with large widths, minimum channel lengths, and an interleaved layout to enhance gain, speed, and margin for differential mismatches. The simplicity of the circuits and the effectiveness of the built-in compensation facilitate analysis. Partitioning and simplifying assumptions are used to thoroughly test the worst case without complex simulations, while providing insight into the design process. Simulated and measured results demonstrate feasibility for 100-mV worst-case sensitivity for CMOS ECL receivers in 1-üm technology, with no substantial accesstime penalty in going from TIL to ECL interfaces. © 1988 IEEE