Evaluation of Cu wiring in a production 64 Mb DRAM

Abstract

This paper presents results evaluating the impact of Copper (Cu) wiring on a production 64 Mb/0.35 μm trench capacitor DRAM technology. There has been considerable progress integrating Cu wiring into high performance logic processes, but little work has been done assessing the viability of Cu integration into a DRAM process. This is an important area of study as performance levels of DRAM technology rise to meet needs such as high bandwidth DRAMs as well as the emerging area of embedded DRAM. Especially for the case of embedding DRAM macros into a logic process, it is important to be able to use high performance wiring technologies using Cu. DRAM processes are extremely sensitive to low levels of metallic contamination, with junction leakage specifications several orders of magnitude lower than those required for high performance logic. Making robust Cu barrier layers is critical. In this work, we demonstrate for the first time that Cu can be integrated into a standard DRAM technology with no degradation in junction leakages or cell data retention time.