1.5-V single work-function W/WN/n+-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM
- Rajesh Rengarajan
- Boyong He
- et al.
- 2002
- IEEE Electron Device Letters
Publications
Date
Featured collections
Popular topics
16 results for C.M. Ransom
Gate-Self-Aligned P-Channel Germanium Misfet's
- Thomas N. Jackson
- C.M. Ransom
- et al.
- 1991
- IEEE Electron Device Letters
Recombination Lifetime Profiling in Very Thin Si Epitaxial Layers Used for Bipolar VLSI
- Paolo Spirito
- S. Bellone
- et al.
- 1989
- IEEE Electron Device Letters
ELECTRICAL CHARACTERIZATION OF SILICON SURFACES EXPOSED TO RIE.
- C.M. Ransom
- P. Spirito
- 1986
- Symposium on Plasma Processing 1986
SHORT-TIME ANNEALING OF DRY-ETCHING DAMAGE.
- C.M. Ransom
- T.O. Sedgwick
- et al.
- 1983
- ECS Meeting 1983
PtSi-Induced Junction Leakage
- J.P. Gambino
- M.D. Monkowski
- et al.
- 2019
- JES
Shallow n+ Junctions in Silicon by Arsenic Gas-Phase Doping
- J.F. DeGeolormo
- D.K. Sodana
- et al.
- 1994
- JES
Recombination Measurement of n-Type Heavily Doped Layer in High/Low Silicon Junctions
- Salvatore Bellone
- Giovanni Busatto
- et al.
- 1991
- IEEE T-ED
IIB-4 Gate-Self-Aligned n-channel and p-channel Germanium MOSFET'S
- C.M. Ransom
- T.N. Jackson
- et al.
- 1991
- IEEE T-ED
Rie-induced damage and contamination in silicon
- Young H. Lee
- G.S. Oehrlein
- et al.
- 1989
- Radiation Effects and Defects in Solids