Conference paper
Modeling parallel computers as memory hierarchies
Bowen Alpern, Larry Carter, et al.
PMMP 1993
Paper
TRIM: Testability Range by Ignoring the Memory
Abstract
The testability by random test patterns of faults in the logic surrounding embedded RAM's is studied. Upper and lower bounds on the probability that a fault is caught are obtained by analyzing a modified, purely combinational circuit without the RAM. This analysis can be done with standard testability analysis techniques. The analysis is applied to an embedded two-port RAM. © 1988 IEEE
Related
Conference paper
Symbolic implication in test generation
Sandip Kundu, I. Nair, et al.
European Conference on Design Automation 1992
D.R. Knebel, P.N. Sanda, et al.
IEEE ITC 1998
Leendert M. Huisman
IBM J. Res. Dev