IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

TRIM: Testability Range by Ignoring the Memory

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The testability by random test patterns of faults in the logic surrounding embedded RAM's is studied. Upper and lower bounds on the probability that a fault is caught are obtained by analyzing a modified, purely combinational circuit without the RAM. This analysis can be done with standard testability analysis techniques. The analysis is applied to an embedded two-port RAM. © 1988 IEEE