Trilayer process for T -gate and Γ-gate lithography using ternary developer and proximity effect correction superposition

Abstract

An alternative method to fabricate T- and Γ-gates used for special geometry compound semiconductor high electron mobility transistors is presented. This method utilizes an acrylate/methylstyrene triple resist stack, a single ternary developer consisting of an acetate/alcohol/water mixture, and a proximity effect correction (PEC) image superposition approach that treats the exposed regions in the different resists as independent images and combines them afterward with weighted factors. In the past, most available options required multiple developers or ebeam exposures to form the resist structure of the gate. In this paper, we present a single developer capable of discriminating among three different resists to form the optimal structure for T- and Γ-gates. The PEC image superposition approach approximates that the exposed regions in each resist layer (or image) can be PEC corrected independently from the other images. The use of a gap between images allows for critical dimension control as image edges are not double exposed due to beam spread. Following gap formation and PEC, the corrected images are superimposed on each other after selectively removing areas of common exposure, using the highest dose as the determining dose. This allows a flexible means to accurately provide PEC to complex structures beyond "simple"T-gates and Γ-gates, as demonstrated in this paper.