Strained Si NMOSFETs for high performance CMOS technology

Abstract

Performance enhancements in strained Si NMOSFETs were demonstrated at Leff <70 nm. A 70% increase in electron mobility was observed at vertical fields as high as 1.5 MV/cm for the first time, suggesting a new mobility enhancement mechanism in addition to reduced phonon scattering. Current drive increase by ≥-35% was observed at Leff <70 nm. These results indicate that strain can be used to improve CMOS device performance at sub-100 nm technology nodes.