Strained-Si devices and circuits for low-power applications

Abstract

Static and dynamic power for strained-Si devices are analyzed and compared with conventional bulk-Si technology. Optimum device design points are suggested by controlling physical/structural device parameters. Strained-Si CMOS circuits are studied, showing substantially-reduced power consumption due to the unique advantageous features of strained-Si devices. The trade-off between power and performance in strained-Si devices/circuits is discussed. Further, analysis and low-power design points are applied and extended to strained Si on SOI substrate (SSOI) CMOS technology.