Statistical exploration of the dual supply voltage space of a 65nm PD/SOI CMOS SRAM cell

This paper describes the application of a novel variability-driven statistical analysis methodology to study the stability/performance of SRAM designs in 65nm PD/SOI technology. Our objective is to explore the design-yield space for wordline and bitline voltage assignments in dual supply SRAM while taking into consideration the impact of random process variations. Two possible scenarios are studied: namely wordline connected to the SRAM cell power supply, and wordline connected to the logic power supply. To the best of our knowledge this is the first time a fully statistical analysis is performed, and results are in excellent agreement with hardware measurements. © 2006 IEEE.