IEDM 1993
Conference paper

SOI for a 1-Volt CMOS Technology and Application to a 512kb SRAM with 3.5 ns Access Time


In this paper a CMOS technology that is optimum for low voltage (in the l-volt range) applications is presented. Thin but undepleted SOI is used as the substrate, which gives low junction capacitance and no body effect. Furthermore floating body effects causes a reduction of subthreshold slope at high drain bias. This lowers the high-VDS threshold to be used, which increases the current drive without significant increase in the off-current.This technology was applied to a high performance 512Kb SRAM. Access time of 3.5 ns at 1 V was obtained.