Simulation and design methodology for a 50-Gb/s multiplexer/demultiplexer package

Abstract

A 50 Gb/s package for SiGe BiCMOS 4:1 Multiplexer and 1:4 Demultiplexer targeting SONET OC-768 Serial Communication Systems is introduced in this work. The package was designed to facilitate bit-error-rate tests and constructed with high-speed coaxial connectors, transmission lines on ceramic substrate, ribbon bonds for chip-to-package interconnects, and a metal composite housing. Numerical simulations were conducted to guide the package design, and both small signal measurements and operational tests were performed thereafter to verify the design and modeling concepts. To keep the model structure under the existing computing capability, the simulation was segmented into three sections-coaxial connector to transmission line, transmission line alone, and transmission line to ribbon bond, and then the results were assembled to predict the performance of the entire package. The package was operated up to 50 Gb/s with low degradation to input digital waveforms and free of error.