About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
DesignCon 2013
Conference paper
Signal and power integrity (SPI) co-analysis for high-speed communication channels
Abstract
The modeling of multiple high-speed chip-to-chip communication links over first (IC package) and second (board) level interconnects is addressed in this paper for data rates up to 28 Gb/s with model-to-hardware correlation. The suggested methodology is based on a bottom-up hybrid approach combining semi-analytical and numerical models, which are able to simultaneously consider the signal and power integrity domains and allow the incorporation of power noise models for the time domain link simulation. The required model complexity and the design space for passive interconnects are explored by analyzing diverse via and channel configurations.