Sharing and Re-use of Statistical Timing Macro-Models across Multiple Voltage Domains

Abstract

This paper presents an approach to solving the problem of generating a single statistical timing macro-model or abstract for a chip component, and subsequently applying it smartly at multiple voltage domain conditions at a parent level of hierarchy during hierarchical timing. This approach avoids overheads in a traditional approach of having either multiple abstracts for the same component corresponding to different voltage domains, or having excessive guard-bands in a single common abstract. Results are presented for a set of test cases including industrial microprocessor units. The results exhibit more than 200 picoseconds of improved accuracy (both pessimism reduction and optimism avoidance) when using the proposed solution in comparison to an approach that assumes a single voltage domain compatible abstract.