Regular logic fabrics for a via patterned gate array (VPGA)

Abstract

Standard-cell-based ASIC costs are increasing so rapidly that fewer products have the volume required to justify NRE costs. Consequently, more designs are relying on programmable devices, such as FPGAs, which have inferior power-delay performance. We propose to explore new regular logic fabrics that are customizable by a few via masks to provide implementation simplicity and NRE costs comparable to an FPGA, but with power-delay performance closer to an ASIC. This paper describes the design of lookup tables (LUTs) similar to those used in FPGAs, but restructured for via-patternability and performance. Results demonstrate power-delay performance comparable to complex-function standard cells, but inferior performance compared to simple logic gates. We compare several logic block designs based on our heterogeneous regular logic fabrics with those constructed using standard cells.