About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
CICC 2003
Conference paper
Scaling beyond the 65 nm node with FinFET-DGCMOS
Abstract
Exponential growth in leakage power density with physical scaling is driving ULSI technology towards innovative device architectures. Double-Gate CMOS (DGCMOS), achieved through use of the Delta Device (1), or FinFET (2), provides both a tactical solution to the gate-leakage challenge and a strategic scaling advantage. FinFET fabrication is very close to that of conventional CMOS process, with only minor disruptions, yielding the potential for a rapid deployment to manufacturing. Planar circuit designs have been converted to FinFET-DGCMOS without disruption to physical area.