The thermal resistance of a three-dimensional (3D) chip stack has been experimentally clarified by authors [1-5] and an additional cooling solution is strongly required to achieve various structures of 3D chip stacks. Especially, when a high heat dissipating chip is located as a bottom chip, cooling from the bottom side of chips (in other words, from the laminate (substrate) side) is identified to be very effective by authors . In this paper, we will describe how to realize effective cooling from the bottom side of chips. A 3D package for high-end server applications is assumed to be composed of a heat-sink, thermal interface material-2 (TIM-2), a heat-spreader (lid), TIM-1, stacked chips, a laminate and a mother board . For effective cooling from the bottom side of chips, the distance between a bottom chip and a bottom-side heatsink should be as short as possible. Therefore, the following three structural improvements are proposed. Firstly, re-distribution layers (RDL) by wafer level packaging (RDL-first process) is adopted to shorten the thickness of the wiring layer (there is no laminates). Secondly, a mother board is drilled and a bottom side heat-sink is embedded in the drilled cavity, where a few layers of circuits (wiring) are kept in a mother board for electrical connections. Thirdly, the joint (interconnection) between a bottom chip and RDL(we call it "Joint-1"), and also the joint between RDL and a mother board (we call it "Joint-2") are shortened as short as possible, such as 25μm. We perform thermal resistance measurement of each component of the proposed package structure, and based on these measured thermal resistances, we demonstrate how much cooling performance is achieved by cooling from the bottom side of chips. It is obtained that the maximum allowable heat density of a bottom chip is 24.5 W/cm2, and it is shown that by further thickness reduction of each component, 44.0 W/cm2 is realized.