Publication
IRPS 2016
Conference paper

Process optimizations for NBTI/PBTI for future replacement metal gate technologies

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Abstract

Bias Temperature Instability (BTI) is a tremendous reliability concern for deeply scaled CMOS technologies, and is the limiting mechanism for further inversion layer thickness (Tinv) scaling for future nodes [1]. Replacement Metal Gate technologies are of particular concern, since the gate stack is not exposed to the high temperature source/drain anneals. We have identified four strategies for reducing BTI in Replacement metal gate technologies: Rapid Thermal Anneal (RTA) optimization, optimization of the HfO2 layer thickness, introducing a gate dielectric dopant for NBTI reduction, and effective Work Function tuning. Judiciously combining these four techniques enable further Tinv scaling for 10 nm and below.

Date

22 Sep 2016

Publication

IRPS 2016

Authors

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