Phase change memory (PCM) is a new solid-state memory technology that promises disruptive changes in the way servers and enterprise storage systems are built. Multilevel-cell (MLC) storage is highly desirable for increasing capacity and thus lowering cost-per-bit in memory technologies. In PCM, MLC storage is hampered by noise and resistance drift. In this paper, the issue of reliability in MLC PCM is addressed. A statistical model is developed that captures the main impairments in MLC PCM cell-arrays. A signal processing and coding framework is then introduced that provides robustness to drift and noise, improving reliability and prolonging data retention. Several examples of codes are provided and practical detection schemes are described.