Multilevel-cell (MLC) storage is a typical way for achieving higher capacity and thus lower cost per bit in memory technologies. In phase-change memory (PCM) MLC storage is seriously hampered by the phenomenon of resistance drift and the impact of temperature. Drift and temperature resilience is achieved through the use of a specific non-resistance-based cellstate metric. A statistical experimental characterization of PCM test devices in the presence of drift and at elevated temperatures is performed, and I-V characteristics are measured. The comparison of conventional resistance and a new enhanced (eM) metric demonstrates for the first time that reliable 2 bits/cell storage and subsequent data retention can be achieved in PCM cell arrays in the presence of temperature variation of the 50 °C magnitude. This development opens up the possibility for practical MLC storage in PCM chips.