PARALLELIZING CIRCUIT SIMULATION USING A COMBINED ALGORITHMIC AND SPECIALIZED HARDWARE APPROACH.

Abstract

Accurate performance estimation for high-density integrated circuits requires detailed numerical simulation. Because of the large computation time required for such programs when they are applied to large circuits, accelerating numerical simulation is an important problem. An approach that exploits the parallelism in the simulation problem at two levels is presented. A relaxation algorithm is used to break the circuit into loosely coupled blocks that can be computed in parallel, and special-purpose hardware is used to exploit parallelism inside the block computation.