RANDOM PATTERN TESTING OF LOGIC SURROUNDING EMBEDDED RAMS USING PERTURBATION ANALYSIS.

Abstract

The effect of a two-port RAM on the random pattern testability of faults in combinational logic preceding the RAM is studied using first-order perturbation theory. This approach takes into account all the statistical dependencies that occur between the output patterns that are read from the RAM during the execution of the test sequence, assuming that the input patterns are random and statistically independent. The approach is shown on a small example to give accurate estimates of the actual exposure probabilities of hard-to-test faults. The same example also shows that ignoring the statistical correlations can lead to large deviations from the exact exposure probabilities when the latter is not close to 0 or 1.