Optimization of high κ gate stacks with poly-Si, FUSI and metal electrodes

Abstract

High k dielectrics and metal gates are the subject of intense investigation as replacements to SiO2-based dielectrics and poly-Si electrodes. High k gates with poly-Si electrodes offer an attractive option for devices that need to operate with low leakage/power loss. We have optimized Hf-based poly-Si/high-k gate stacks to suppress large Vt shifts commonly observed in pFET devices. In addition, we have achieved excellent electron mobilities in poly-Si gated high k stacks - 90-100% of SiON - paving the way for implementation in low power technologies without compromising on device performance. Optimizing poly-Si pre-doping techniques, high k devices at Tinv ∼16.5A were also fabricated with fully suicided (FUSI) electrodes that offer up to ∼350 mV of Vt tuning in n- and p FET directions. A key impediment in realization of metal gated high k devices is the unacceptably high loss in electron mobility that makes the devices impractical. By careful optimization of the gate stack and the interface layers, we have demonstrated that high electron mobilities - close to conventional poly-Si gated SiON - can be achieved in metal gated stacks. Our measurements indicate low interface state densities, excellent breakdown reliability and Vt stability over 10 years for these stacks.