Massive E-beam Metrology Characterization of Reticle Stitching Boundaries

Abstract

With the increase in processing power and performance needed for system-on-chip AI architectures and interposers, large-format chips are becoming more prevalent in production. Contrary to this, the introduction of the first High-NA EUV tool demonstrates half the prior achievable single exposure field size, which is unable to pattern an entire large-format chip in one exposure. Multi-reticle stitching, the process by which distinct reticles are used in a single printing layer to create interwoven and connected patterns, can be used to expose an entire chip that is larger than a single reticle size. However, overlay between the reticles must be tight to maintain control over the overlapping exposure boundaries needed to create electrical connections between the independent reticle patterns at the stitch boundary. We use a massive e-beam inspection platform with CAD-based measurement models, which simulate the incoming reticles independently, to image and measure stitch boundaries on a variety of electrical features utilizing programmed translation, magnification, and rotation reticle to reticle offsets. The CAD-based model independently extracts the offsets of stitched feature.