Junction profiling on hot carrier stressed device by dual lens electron holography and scanning capacitance microscopy

Abstract

Hot carrier stress is one of the key parameter for CMOS device reliability in semiconductor manufacturing process. Electron holography and scanning capacitance microscopy are used to map the junction for hot carrier stressed and unstressed device. Junction asymmetry is observed for the stressed device comparing with unstressed device, which indicates dopant deactivation (or movement) during the stress and it is contrary to the early proposed mechanism of carrier injection into gate oxide during the stress causing gate oxide damage. Based on that observation, we propose hydrogen atom released from the hot carrier stress de-activates phosphorus dopant on the drain side, which causes lower drive current.