While semiconductor logic device nodes keep moving to N3 and beyond, the backend of line (BEOL) metal pitch is aggressively scaling to improve device performance and density. BEOL damascene extension refers to interconnect with a full metal pitch of 26-21 nm. The challenges of damascene extensions are profoundly critical due to an extreme ultraviolet (EUV) single exposure limit, dielectric etch, and metallization challenges. Multipatterning is required as well as more advanced low K dielectric etch. Severe line wiggling, bad via/contact hole open, and via/trench short issue can easily be observed. Cu resistance also contributes to most of the device’s R/C delay. Before transitioning to subtractive metal integrations, there is no doubt that multipatterning damascene extension plays an important role in bridging the gap between them. In this work, we provide an in-depth feasibility study on damascene extension focusing on EUV self-aligned double patterning with cut and block assembly for 24 nm pitch line and space. EUV double patterned self-aligned via is also validated for the dual damascene test. Both continuous wave and quasiatomic layer etch are developed to achieve a wiggling-free, bridge-free, and high metal hard mask selectivity process in TEL’s new generation capacitively coupled plasma etchers. Copper metallization is demonstrated in both via and trench of a 24 nm pitch. This report provides an important insight into damascene extension feasibility for high volume manufacturing.