As contact dimensions continue to shrink to support scaling, local CD variation (LCDU) becomes a critical driver of electrical variation and defectivity. Continued logic scaling is highly dependent on middle of line (MOL), which further amplifies the need for LCDU improvement. LCDU improvement will be critical to improving edge placement error (EPE). The same concepts can also be applied to back end of line (BEOL) vias. Since lithography tools are unable to consistently print contacts below 20 nm, it is typically necessary to shrink through etch. There are various etch techniques we can use to shrink contact dimensions each having different impacts on LCDU and defectivity. In this study we explore the impacts of various shrink methods to optimize LCDU and defect density. In this study a simple patterning stack of SiN + OPL + ARC + resist is used to simulate contact patterning. Various etch chambers and shrink techniques are used to reach a target CD range and LCDU and defect density are evaluated. The chambers evaluated include TEL's conductor etcher and TEL's dielectric etcher. LCDU data is collected using CDSEM. Defect density is evaluated using various etch techniques. Etch techniques such as deposition on resist, ARC and OPL, descum steps, pulsing and quasi atomic layer etch are explored. Multiple types of deposition techniques are used including selective deposition and cyclic deposition and trim. These techniques are optimized to be sensitive to open area and correct for local CD variations. On wafer LCDU performance of <2.0nm is demonstrated and further optimization is done to minimize defectivity.