Abstract
IBM 'Telum', the latest microprocessor for the next generation IBM Z system has been designed to improve performance, system capacity and security over the previous enterprise system [1].The system topology has changed from a two-design strategy featuring one central system-controller chip (SC) and four central-processor (CP) chips per drawer into a one-design strategy, featuring distributed cache management across four Dual-Chip Modules (DCM) per drawer, each consisting of two processor chips for both core function and system control. The CP die size is 530mm2 in 7nm bulk technology [5] [6].The system contains up to 32 CPs in a four-drawer configuration (Fig 2.3.1). Each CP (shown in Fig 2.3.2 die photo) contains 22B transistors, operates at over 5GHz and is comprised of 8 cores, each with a 128KB L1 instruction cache, a 128KB L1 data cache and a 32MB L2 cache. Chip interfaces include 2 PCIe Gen4 interfaces, an M-BUS interface to the other CP on the same DCM and 6 X-BUS interfaces connecting to other CP chips on the drawer.6 out of the 8 CPs in each drawer have an A-Bus connection to the other drawers in the system.