Hotspot-optimized interlayer cooling in vertically integrated packages

Abstract

High-performance, vertically integrated chip stacks with multiple logic layers and aligned hot spots, need cooling by an interlayer heat-removal approach. At high interconnect densities, fluid friction increases dramatically, and the most significant portion of the junction temperature rise is due to a sensible heat increase in the fluid. First we introduce three building blocks that extend the interlayer cooling capability to an interconnect pitch less than 100μm by considering hot-spot-aware mass and heat transfer. The methods used are hydraulic diameter modulation, four-port fluid access, and fluid focusing. Second, we demonstrate an approach to combine these methods based on an efficient porous-medium approach using expressions for pressure gradients and convective thermal resistances derived from detailed sub-modeling in communicating pin fin array cavities. Finally, three different global heat-transfer layouts are compared. © 2009 Materials Research Society.