FinFET performance advantage at 22nm: An AC perspective

Abstract

At the 22 nm node, we estimate that superior electrostatics and reduced junction capacitance in FinFETs may provide a 13∼23% reduction in delay relative to planar FETs. However, this benefit is offset by enhanced gate-to-source/drain capacitance (Cgs) in FinFETs. Here, we measure FinFET Cgs capacitance at 22nm-like dimensions and determine that, with optimization, the FinFET capacitance penalty can be limited to <6%, resulting in an overall advantage of up to 17% over a planar technology. © 2008 IEEE.