Dynamic body charge modulation for sense amplifiers in partially depleted SOI technology

We present a dynamic body charge modulation technique to improve the matching of CMOS device threshold voltage (V t) characteristics in the partially depleted silicon-on-insulator (SOI) technology. For a latch-type sense amplifier in the SRAM complementary bitline structure, a pair of charging FETs are employed to bring the bodies of cross-coupled sensing devices to the voltage rail. In doing so, operating history-dependent body potential mismatches are eliminated for every access cycle. Body-contacted FETs are returned to their floating body states when the charging action is completed. This technique achieves repeatable low-V t and high-performance operation simultaneously. The pulse signal controlling body charging is not constrained by a stringent timing requirement. Therefore, its effectiveness is insensitive to the body contact quality of sensing FETs. This technique demonstrates a significant leverage for high-performance RAM circuits. It also offers the advantages of speed and noise immunity in the low-voltage low-power operating regime.