Sub-400-ps ISL circuits

Abstract

This paper describes advanced Integrated-Schottky-Logic (ISL) circuits featuring double-poly self-alignment, “free” epi-base lateral p-n-p clamp, Selfaligned guard ring Schottky barrier diode, and silicon-filled trench isolation. Using a 0.7-µm-thick epitaxial layer and 1.2-µm minimum dimensions, gate delays of 432 ps (fan-out = 1) and 527 ps (fan-out = 3) are obtained at current levels of 183 and 255 µA/gate, respectively, with nonwalled emitter. With walled emitter (two sides), a gate delay of 382 ps is achieved for fan-out of 3 at a current level of 267 μA/gate. © 1986 IEEE