Jih-Kwon Peir, Windsor W. Hsu, et al.
EuroSys 2008
In this correspondence, we propose design techniques that may significantly simplify the cache access path, and hence offer the opportunity of shorter cycle time or fewer pipeline stages. Our proposals are based on highly accurate prediction methods that allow us to efficiently resolve address translation information early in the pipe. © 1993 IEEE
Jih-Kwon Peir, Windsor W. Hsu, et al.
EuroSys 2008
Jih-Kwon Peir, Yongjoon Lee, et al.
EuroSys 2008
Jih-Kwon Peir, Windsor W. Hsu, et al.
Journal of Systems Architecture
Jih-Kwon Peir, Yann-Hang Lee
SPDP 1990