CMOS scaling into the nanometer regime

Abstract

Starting with a brief review on 0.1-μm (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations, and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may take us to the outermost limits of silicon scaling. Keywords - CMOS integrated circuits, integrated circuits, MOS-FET logic devices, MOSFET's, transistors, very-large-scale integration. © 1997 IEEE.