An energy-efficient and multi-bit (4b) current-based analog compute in-memory (CIM) architecture is proposed in this paper. In current-based analog CIM schemes, multiplication and-accumulate (MAC) operation is performed on bitline, and resultant output is equivalent to bitline voltage drop (ΔVRBL). However, dependence of ΔVRBL on process, voltage and temperature (PVT) variations and analog non-idealities (ANIs), reduces the signal-to-noise ratio (SNR) of MAC and degrade the computation accuracy of MAC in analog CIM architecture. An analytical model of ΔVRBL to predict the computation accuracy of MAC in current-based analog CIM architecture through a single SPICE simulation is presented in this paper. The proposed model determines the dynamic range of analog input voltage (Va) on the bitline for linear MAC operation for a given technology node. This model also provides a design methodology to predict computation accuracy of MAC and optimize design parameters for current-based analog CIM architecture with the modelling error of 1.1% in SPICE simulations. The implementation of the proposed CIM architecture and model validation are done using a standard 65nm CMOS technology. The proposed architecture achieves 13× energy-efficiency and 2.5× reduction in latency for 4-b multiplication and accumulation (MAC) operation than state-of-the-art. The proposed CIM architecture achieves 13× improvement in Figure of Merit (FoM).