In this brief, we present an energy-efficient and high compute signal-to-noise ratio (CSNR) XNOR and accumulation (XAC) scheme for binary neural networks (BNNs). Transmission gates achieve a large compute signal margin (CSM) and high CSNR for accurate XAC operation. The 10T1C XNOR SRAM bit-cell performs the in-memory XAC operation without pre-charging the larger bitline capacitances and significantly reducing energy consumption per XAC operation. The validation of the proposed XAC scheme is done through the post-layout simulations in 65nm CMOS technology with VDD of 1 V. The achieved 1 ns of latency and 2.36 fJ of energy consumption per XAC operation are ( 7.2×, 7.2×) and (2×, 1.31×) lower than state-of-the-art digital and analog compute in-memory (CIM) XAC schemes respectively. The proposed XAC design achieves 8.6 × improvement in figure-of-merit (FoM), over prior state-of-the-art. Moreover, (σ/μ) average of 0.2% from Monte Carlo simulations show that proposed XAC scheme is robust against systematic mismatch and process variations.