Gate resistance, middle of line resistance, and back end of line resistance in modern metal-gate CMOS increase drastically as the dimensions of the gates, interconnects and vias scale down close to or below the bulk electron mean free paths (MFPs) of the metal materials. These resistances, especially the gate resistance, impose more and more significant RC delay to CMOS circuits and become significant concerns in sub-22-nm CMOS. In order to optimize the metal-gate materials and structures for low resistance, accurate metal resistance model is needed. In this letter, we propose an analytical metal resistance model applicable for metal wires and films even with sub-MFP sizes. Our model includes scattering effects from surfaces, interfaces, and grain boundaries, and has been successfully verified on W metal gates with the feature sizes ranging from 20 to 70 nm.