Al Coverage of Surface Steps at SiO2 Insulated Polycrystalline Si Boundaries: Al Evaporation in Vacuum and Low Pressure Ar

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In integrated circuit technology, a potential reliability problem arises due to voids that form in aluminum interconnection lines where they cross the SiO2-insulated polycrystalline silicon (polysilicon) regions. Not only do these voids cause thinning of the Al lines which may then burn out at high current densities, but the voids are also potential sites for accumulation of chemical residues which could lead to a long term deterioration of the integrated circuit. This study examined the formation and structure of step profiles at SiO2-insulated polysilicon boundaries and voids in Al lines crossing the boundaries. The formation and structure were studied as a function of process variables including delineation of the polysilicon boundary, chemical vapor deposition or thermal growth of the SiO2 insulation, evaporation of the Al layer, and delineation of the Al line pattern. The addition of Ar gas at a pressure of 0.1 to 10 milliTorr to the Al evaporation chamber resulted in excellent step coverage and eliminated the Al void formation, even in the case of very steep step profiles. © 1979, The Electrochemical Society, Inc. All rights reserved.


09 Dec 2019