IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

A timing analysis algorithm for circuits with levelsensitive latches


For a logic design with levelsensitive latches, we need to validate timing signal paths which may flush through several latches. We developed efficient algorithms based on the modified shortest and longest path method. The computational complexity of our algorithm is generally better than that of known algorithms in the literature. The implementation (CYCLOPSS) has been applied to an industrial chip to verify the clock schedules. © 1996 IEEE.